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What is axi-compliance-skill?

ruihongy/axi-compliance-skill — explained in plain English

Analysis updated 2026-05-18

32PythonAudience · developerComplexity · 3/5LicenseSetup · easy

In one sentence

Claude skills that check Verilog and SystemVerilog hardware code against ARM AXI bus protocol specifications.

Mindmap

mindmap
  root((AXI Compliance))
    What it does
      Checks AXI RTL code
      Reports violations
      Suggests fixes
    Tech stack
      Python
      Verilog
      SystemVerilog
    Use cases
      Protocol compliance checks
      Assertion templates
    Audience
      Hardware engineers
      Chip designers

Code map

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What do people build with it?

USE CASE 1

Check AXI4-Stream or AXI4-Lite Verilog code against the ARM specification automatically.

USE CASE 2

Get a severity-ranked report of critical, warning, and informational protocol issues.

USE CASE 3

Receive a corrected code snippet for every critical protocol violation found.

USE CASE 4

Drop generated SystemVerilog assertion templates into a testbench for ongoing checks.

What is it built with?

PythonSystemVerilogVerilog

How does it compare?

ruihongy/axi-compliance-skillautolearnmem/automembilly-ellis/exr-imageio-poc
Stars323232
LanguagePythonPythonPython
Setup difficultyeasyhardmoderate
Complexity3/55/53/5
Audiencedeveloperresearcherresearcher

Figures from each repo's GitHub metadata at analysis time.

How do you get it running?

Difficulty · easy Time to first run · 5min

Install the .skill file through Claude's settings, then paste RTL code into a conversation.

Use freely for any purpose, including commercial use, as long as you keep the copyright notice.

So what is it?

AXI Compliance Skills is a set of add-on skills for Claude that review hardware description code, specifically Verilog and SystemVerilog, against published ARM AMBA protocol specifications. The intended audience is hardware engineers writing digital logic that must communicate over AXI-family buses, which are a standard way for components on a chip to exchange data. The repository currently includes two skills. The first, axi4-stream-compliance, checks code against the AXI4-Stream specification and covers 25 rules across eight categories: handshake behavior, reset conditions, signal stability, data widths, keep and strobe signal usage, last-frame framing, combinatorial dependency issues, and optional signal handling. The second, axi4-lite-compliance, checks against the AXI4-Lite specification and covers 30 or more rules across eight categories: per-channel handshake for each of the five protocol channels, reset, signal stability, address alignment, response codes including one response type that is illegal in the Lite subset, inter-channel ordering, and detection of signals that belong only to the full AXI4 spec. Each skill produces a structured report with three severity levels: critical for direct violations that cause data loss or functional failure, warning for patterns that risk interoperability problems, and informational for best-practice suggestions. For every critical finding, the skill provides a corrected code snippet and a SystemVerilog assertion template ready to drop into a testbench. To use a skill, download the skill file, install it through Claude's settings, then paste RTL code into a conversation and ask Claude to check it. Claude detects which AXI signals are present and applies the appropriate skill automatically. The repository is MIT licensed and based on ARM AMBA specifications IHI0051 and IHI0022.

Copy-paste prompts

Prompt 1
Check this AXI4-Lite slave module for protocol compliance using the axi-compliance-skill.
Prompt 2
Explain what the axi4-stream-compliance skill checks for TLAST framing.
Prompt 3
Walk me through installing these Claude skills from the .skill files.
Prompt 4
What response codes are illegal in the AXI4-Lite subset according to this skill?

Frequently asked questions

What is axi-compliance-skill?

Claude skills that check Verilog and SystemVerilog hardware code against ARM AXI bus protocol specifications.

What language is axi-compliance-skill written in?

Mainly Python. The stack also includes Python, SystemVerilog, Verilog.

What license does axi-compliance-skill use?

Use freely for any purpose, including commercial use, as long as you keep the copyright notice.

How hard is axi-compliance-skill to set up?

Setup difficulty is rated easy, with roughly 5min to a first successful run.

Who is axi-compliance-skill for?

Mainly developer.

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