ruihongy/axi-compliance-skill — explained in plain English
Analysis updated 2026-05-18
Check AXI4-Stream or AXI4-Lite Verilog code against the ARM specification automatically.
Get a severity-ranked report of critical, warning, and informational protocol issues.
Receive a corrected code snippet for every critical protocol violation found.
Drop generated SystemVerilog assertion templates into a testbench for ongoing checks.
| ruihongy/axi-compliance-skill | autolearnmem/automem | billy-ellis/exr-imageio-poc | |
|---|---|---|---|
| Stars | 32 | 32 | 32 |
| Language | Python | Python | Python |
| Setup difficulty | easy | hard | moderate |
| Complexity | 3/5 | 5/5 | 3/5 |
| Audience | developer | researcher | researcher |
Figures from each repo's GitHub metadata at analysis time.
Install the .skill file through Claude's settings, then paste RTL code into a conversation.
AXI Compliance Skills is a set of add-on skills for Claude that review hardware description code, specifically Verilog and SystemVerilog, against published ARM AMBA protocol specifications. The intended audience is hardware engineers writing digital logic that must communicate over AXI-family buses, which are a standard way for components on a chip to exchange data. The repository currently includes two skills. The first, axi4-stream-compliance, checks code against the AXI4-Stream specification and covers 25 rules across eight categories: handshake behavior, reset conditions, signal stability, data widths, keep and strobe signal usage, last-frame framing, combinatorial dependency issues, and optional signal handling. The second, axi4-lite-compliance, checks against the AXI4-Lite specification and covers 30 or more rules across eight categories: per-channel handshake for each of the five protocol channels, reset, signal stability, address alignment, response codes including one response type that is illegal in the Lite subset, inter-channel ordering, and detection of signals that belong only to the full AXI4 spec. Each skill produces a structured report with three severity levels: critical for direct violations that cause data loss or functional failure, warning for patterns that risk interoperability problems, and informational for best-practice suggestions. For every critical finding, the skill provides a corrected code snippet and a SystemVerilog assertion template ready to drop into a testbench. To use a skill, download the skill file, install it through Claude's settings, then paste RTL code into a conversation and ask Claude to check it. Claude detects which AXI signals are present and applies the appropriate skill automatically. The repository is MIT licensed and based on ARM AMBA specifications IHI0051 and IHI0022.
Claude skills that check Verilog and SystemVerilog hardware code against ARM AXI bus protocol specifications.
Mainly Python. The stack also includes Python, SystemVerilog, Verilog.
Use freely for any purpose, including commercial use, as long as you keep the copyright notice.
Setup difficulty is rated easy, with roughly 5min to a first successful run.
Mainly developer.
This repo across BitVibe Labs
Verify against the repo before relying on details.