What is tiny-gpu?

tiny-gpu is a small, educational GPU design written in Verilog, built to teach how graphics processing units work at the hardware level rather than at the level of writing programs for them. While CPUs are well documented and easy to learn about from architecture down to control signals, real GPU designs are kept proprietary by manufacturers, so there is very little material showing how they actually work inside. This project strips away the complexity of a production graphics card and keeps only the core ideas shared by GPUs and other modern accelerators like Google's TPU: how the architecture is organized, how the parallel programming model called SIMD is implemented in hardware, and how a GPU deals with limited memory bandwidth. This particular repository is a fork of an earlier project by another author, and it is careful to credit that original work for the architecture, instruction set, hardware description, and documentation. The fork adds several things the original README asked contributors to build next. It rewrites the original SystemVerilog code into a more portable form of Verilog from 2005, and adds a full path for turning the design into an actual chip: synthesis and test scripts for a professional Cadence toolchain, an equivalent open-source flow using LibreLane targeting the sky130 chip process, and a complete adapter for TinyTapeout, a program that lets hobbyists get small designs manufactured as real silicon. That adapter includes on-chip program and data memory, a way to load programs one byte at a time from a host computer, a smaller GPU configuration sized to fit the TinyTapeout constraints, a MicroPython driver for controlling it from a host, and the manufacturing-ready files needed for tapeout. The GPU itself runs one kernel at a time. Launching a kernel means loading program memory with instructions, loading data memory with the values to process, telling the device how many threads to run, and then starting it. Internally it consists of a device control register, a dispatcher that splits threads into groups called blocks and hands them to available compute cores, one or more compute cores that each run a block of threads with their own arithmetic unit, load and store unit, program counter, and registers, separate memory controllers for program and data memory that throttle requests to match real memory bandwidth, and a cache, still a work in progress, meant to avoid repeatedly fetching the same data from external memory. The project includes working matrix addition and multiplication example programs along with support for simulating and tracing kernel execution.