Simulate and study a working 5-stage pipelined RISC-V processor for a computer architecture course.
Use it as a base design to synthesize and run a simple RISC-V CPU on an FPGA.
Learn RTL design and verification practices through a modular, real processor implementation.
Extend the processor with additional RISC-V instructions or new architectural features.
| dakshlohchab/risc_v_32i | alisharafiiii/sauron-eye | code-my-spec/ear_witness | |
|---|---|---|---|
| Stars | 2 | 2 | 2 |
| Language | C | C | C |
| Setup difficulty | hard | hard | hard |
| Complexity | 4/5 | 5/5 | 4/5 |
| Audience | researcher | developer | developer |
Figures from each repo's GitHub metadata at analysis time.
Requires Xilinx Vivado for simulation and synthesis, plus RTL design familiarity.
This project is an implementation of a computer processor built from scratch, following the RISC-V RV32I instruction set, a well known open standard for how a simple 32 bit CPU should understand and execute instructions. It is written in SystemVerilog, a hardware description language used to design chips, rather than a programming language meant to run on an existing computer. The processor uses a five stage pipeline, meaning it breaks the work of running an instruction into five steps: fetching the instruction from memory, decoding what it means, executing the actual calculation, accessing memory if needed, and writing the result back to a register. Each stage is built as its own separate module, and dedicated registers pass information between stages, which lets the processor work on several instructions at once instead of waiting for each one to fully finish before starting the next. The design supports a solid range of RV32I instructions, including basic arithmetic like addition and subtraction, logical operations such as AND and OR, shifts, comparisons, memory loads and stores, branches, and jumps. It is built to be modular, so each piece can be understood, tested, and modified on its own, and the author designed it with an eye toward being extended later with more advanced features. This is meant to be simulated and synthesized using Xilinx Vivado, a professional tool for designing chips that can run on FPGAs, which are reprogrammable hardware chips. It is best suited for students and hobbyists studying computer architecture, people learning RTL design and verification, or anyone experimenting with building their own RISC-V processor. The README notes that no specific open-source license has been chosen yet, so anyone wanting to reuse or distribute this work should check with the author first.
A modular 5-stage pipelined RISC-V RV32I processor built in SystemVerilog for FPGA simulation and learning computer architecture.
Mainly C. The stack also includes SystemVerilog, Xilinx Vivado, FPGA.
The README says no specific open-source license has been chosen yet, so reuse or distribution terms are unclear.
Setup difficulty is rated hard, with roughly 1day+ to a first successful run.
Mainly researcher.
This repo across BitVibe Labs
Verify against the repo before relying on details.