What is jyd-rv32i-fpga-core?

This repository contains the design for a small CPU that can be loaded onto an FPGA chip, built as an educational project for a Chinese RISC-V design contest called JYD. RISC-V is an open standard for how a processor understands instructions, and RV32I is the simplest version of it, covering 32 basic integer operations. An FPGA is a chip whose internal logic can be reprogrammed, making it a common learning tool for designing hardware from scratch. The CPU is written in SystemVerilog, a hardware description language, and the project includes everything needed to reconstruct the Vivado project file used by Xilinx FPGA tools. The repository layout separates the CPU logic into pipeline stages (fetch, decode, execute, load/store, writeback), a peripheral bridge for connecting to things like LEDs and a seven-segment display, and testbench files for running simulations. The memory map is documented: program code lives at one address range, data at another, and small peripherals like switches, keys, and the display are mapped to fixed addresses. The README is careful about what the project does and does not claim. A private simulation run observed the CPU passing all 37 instructions targeted by the contest, but the memory initialization files used for that run are not included in the public repository. What is included are several simpler self-generated test programs that check basic things like memory writes and branch instructions, but these are explicitly described as smoke tests, not full instruction coverage. Setting up requires Xilinx Vivado software and either a set of private memory files (contest-specific, not redistributed) or the included public smoke memory files. A Tcl script recreates the Vivado project from the repository files. Python scripts generate the public test memory images. A PowerShell script checks the repository is clean before submission. The project is in early-stage preview and the authors are explicit that it is not production-ready, not formally verified, and not intended as a reference core for others to build on. It is organized for students learning digital design and hardware description languages.